Frequently Asked Questions
Everything you need to know about AgentIC, local EDA automation, supported PDKs, and pricing.
What is AgentIC?
AgentIC is an AI-powered VLSI design agent that automates RTL-to-GDSII chip design flows. It bridges large language models with local Electronic Design Automation (EDA) tools and Process Design Kits (PDKs) to autonomously write, verify, and harden digital and analog designs.
What PDKs does AgentIC support?
AgentIC supports SkyWater Sky130, GlobalFoundries GF180MCU, ASAP7, and Nangate45 as open-source PDKs. Any proprietary PDK (TSMC, Intel, Samsung) can be used via local installation. The agent discovers available PDKs automatically and asks the user which to target.
Can AgentIC design analog circuits?
Yes. AgentIC supports analog and mixed-signal design via SPICE netlist generation and simulation with ngspice (open source) or Spectre, Eldo, HSPICE, and Xyce (proprietary). It uses real PDK transistor primitives (e.g. sky130_fd_pr__nfet_01v8) and can run DC, AC, transient, and Monte Carlo analyses. Schematic capture is supported via xschem.
What EDA tools does AgentIC work with?
AgentIC works with both open-source and proprietary EDA tools. Open-source: Yosys (synthesis), Verilator/iverilog (simulation), OpenROAD (physical design), OpenSTA (timing), Magic/KLayout/Netgen (DRC/LVS), ngspice (SPICE simulation). Proprietary: VCS, Xcelium, Questa (simulation), Design Compiler/Genus (synthesis), Innovus/ICC2 (PnR), PrimeTime/Tempus (STA), Calibre (DRC/LVS).
What operating systems does AgentIC support?
AgentIC natively supports Linux and macOS (Apple Silicon & Intel). The desktop app is Electron-based with a local Python backend that interacts directly with your local EDA tools and PDKs.
Is my chip design data sent to the cloud?
No. AgentIC is local-first. Your RTL, netlists, PDK files, simulation logs, and design artifacts never leave your machine. The only external calls are to your configured LLM provider (for agent reasoning) and the license server (for entitlement verification). You can use a local LLM (e.g. Ollama) for zero data leaving your machine.
How does AgentIC verify its designs?
AgentIC follows a real VLSI verification methodology: it lints every RTL file after writing (verilator/iverilog), simulates with testbenches, runs synthesis with SDC constraints, performs STA with real parasitics, and executes DRC/LVS/antenna checks before declaring a design complete. An auto-checkpoint engine parses EDA logs and returns structured pass/fail verdicts.
How does AgentIC handle SRAMs and memories?
AgentIC never infers large memories as flip-flop arrays. It queries the PDK capability graph for available compiled SRAM macros (e.g. sky130_sram_2kbyte_1rw1r_32x512_8), instantiates the real macro in a wrapper, and uses black-box synthesis with the macro's Liberty file. If no macro exists, it proposes OpenRAM compilation or asks the user.
Can AgentIC integrate third-party SystemVerilog IP?
Yes. AgentIC uses sv2v (the open-source SystemVerilog-to-Verilog converter) to convert .sv IP for Yosys synthesis, and Verilator for native SystemVerilog simulation. It never hand-rolls custom preprocessors.
What is the difference between AgentIC and a generic coding agent?
Generic coding agents treat VLSI output as plain text and dump raw terminal logs into the LLM context. AgentIC has a local backend runtime that parses gigabytes of EDA logs into structured verdicts, maintains a durable checkpoint engine for state recovery, indexes PDK cell libraries for grounding, and enforces VLSI quality gates (behavioral memory rejection, non-synthesizable construct detection, one-module-per-file, structural top-level). It is purpose-built for chip design.
How much does AgentIC cost?
AgentIC can be downloaded and used without a license key or account. If AgentIC ever introduces paid plans in the future, the pricing page will be updated accordingly.
Where can I download AgentIC?
AgentIC can be downloaded from https://buildstack.live/agentic/download. Builds are available for macOS (.dmg) and Linux (.AppImage, .deb).